The present invention relates in general to integrated circuits, and more particularly to memory arrays in integrated circuits. Still more particularly, the present invention relates to address buffers. 2. Description of the Prior Art
Address buffers are used in many circuits, with one example being memory arrays. Address buffers are used, in conjunction with decoders, to select row or bit lines within a memory array. Usually only a certain number of row and bit lines may be selected at any point in time.
For some test or operating modes of the memory array, however, selection of all or a portion of row and/or bit lines at a single time is desirable. An example of a test mode where selecting all or a portion of the row and bit lines at a single time is necessary is described in co-pending U.S. patent application Ser. No. 07/954,276, entitled Stress Test For Memory Arrays In Integrated Circuits, filed Sep. 30, 1992. A plurality of rows are selected at one time and a stress voltage is placed on a plurality of bit and complementary bit lines. In this manner the memory cells within the memory array are stress tested in order to detect latent defects.
Another example of a test mode where selecting all of the row and bit lines at a single time is necessary is described in co-pending U.S. patent application Ser. No. 08/05,376, entitled Method for Testing Stress Decoders And Periphery Circuits, filed Apr. 30, 1993. A plurality of rows and bit lines are selected or deselected simultaneously and a stress voltage is applied to the integrated circuit. In this manner, latent defects within the decoders and periphery circuits can be detected.
Therefore, it is desirable to provide a circuit which allows for the simultaneous selection or deselection of a plurality of rows and columns within a memory array. It is also desirable that such a circuit be compact and not significantly affect the normal operation of the integrated circuit.